(a) Field of the Invention
The present invention relates to a non-volatile memory device and a method for manufacturing the same. More particularly, the present invention relates to a non-volatile memory device providing two bits per cell and having an enhanced programming capacity and efficiency, and a method for manufacturing the same.
(b) Description of the Related Art
In a non-volatile memory device (among various semiconductor memory devices), data are not erased even when power is turned off.
At present, the non-volatile memory devices are divided into floating gate memory devices, and MIS (metal-insulator-semiconductor) memory devices in which two or more kinds of dielectric layers are stacked to form a double layer or a triple layer.
The floating gate non-volatile memory devices realize their memory characteristic using a potential well. The MIS non-volatile memory devices realize their memory characteristic using a trap existing in an interface (e.g., a charge trapping or charge storage capability provided by certain materials and/or the interface between them).
For a MIS non-volatile memory device, a silicon-oxide-nitride-oxide-semiconductor (SONOS) structure is widely adopted.
A typical structure of a conventional planar type SONOS device is illustrated in FIG. 1.
As shown in FIG. 1, according to a conventional SONOS device, a first oxide layer 2, a nitride layer 3, and a second oxide layer 4 are stacked on a semiconductor substrate 1 in an oxide-nitride-oxide (ONO) structure 5, and a gate 6 is formed thereabove. A source 7 and a drain 8 are formed in the semiconductor substrate 1 at positions or locations horizontally external to the gate 6.
An advance to such a conventional SONOS structure concerns a 2-bit/cell structure providing two bits per cell, introduced to increase memory capacity with the same gate width.
FIG. 2 is a cross-sectional view of a conventional SONOS device in a 2-bit/cell structure. As shown in FIG. 2, a gate 12 is formed above a semiconductor substrate 10, and a first oxide layer 11 is formed between the gate 12 and the semiconductor substrate 10 and at each lateral side of the gate 12.
A nitride layer 13 is formed lateral to the first oxide layer 11 (that was formed laterally to the gate 12). The gate 12 is further provided with a second oxide layer 14 that covers the nitride layer 13. A source 15 and a drain 16 are formed in the semiconductor substrate 10 at positions horizontally external to the gate 12.
However, charges may not be effectively trapped under all circumstances in such a 2-bit/cell structure since an area for trapping the charges is small.
Furthermore, when the first oxide layer is degraded, charges may escape to the substrate while storing programmed data. In this case, a threshold voltage Vth of the transistor device may be lowered, and thus a ΔVth may decrease. Here, the ΔVth denotes a voltage difference between threshold voltages Vth in a forward bias and a reverse bias. A reduction of ΔVth level may cause a problem of an over-erase, and therefore, the ΔVth is recommended to remain as constant as possible.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore, it may contain information that does not form prior art that may be already known in this or another country to a person of ordinary skill in the art.